ADSP-TS101 高速全双工 Link 收发器 FPGA 设计

Design of ADSP-TS101 High-Speed Full-Duplex Link Transmitter FPGA

摘要: 提出并实现了一种基于 ADI TigerSHAＲC101 Link 协议的高速通信收发器TPGA设计方案，能同时在接口时钟的上升沿和下降沿收发数据，进而实现 FPGA 与 DSP、以及 FPGA 片间的无缝连接．经 ISE 综合与布局布线验证，整个系统仅占用452个 Slice，最高工作频率超过300MHz，数据传输率可达 4.8 Gb/s．

Abstract: A high-rate transceiver FPGA strategy based on ADI TigerSHARC101 Link protocol was presented, which can complete data exchange both on rising edge and falling edge of interface clock, The seamless connection between FPGA and DSP/FPGA was achieved. After ISE synthesis and routing, the highest work clock of whole system can achieve 300 MHz, with only 452 slices utilized. The equivalent transmitting rate was 4.8 Gb/s